The invention relates to a switching system for an asynchronous transfer mode (ATM) switch duplexed in an apparatus. More particularly, the invention relates to a hitless switching system for an ATM switch having the function of discard priority control.
Japanese Patent Laid-Open No. 83529/1997 discloses, as this type of a conventional switching system for an ATM switch, xe2x80x9cATM cell flow controllerxe2x80x9d that realizes hitless switching in a duplexed transmission path. In this ATM cell flow controller, received signals of two systems having respective phases shifted due to the influence of a difference in path between duplexed transmission paths are subjected to delay adjustment to equalize the duplexed received signals to each other in the same phase, thus realizing hitless switching. A phase comparator circuit is disposed between a polishing circuit to avoid such an unfavorable phenomenon that the phase comparator is not properly operated due to the influence of cell discard created in the polishing circuit.
Further, Japanese Patent Laid-Open No. 186575/1996 discloses a xe2x80x9chitless switching systemxe2x80x9d that can realize hitless switching of duplexed transmission paths. In this hitless switching system, as with the above conventional ATM cell flow controller, received signals of two systems respectively having shifted phases are subjected to delay adjustments to equalize duplexed received signals in the same phase, thus realizing hitless switching. Further, phase comparison is performed based on received time of a monitoring cell inserted by a transmitter provided upstream of the transmission path.
Japanese Patent Laid-Open No. 139726/1996 discloses an xe2x80x9cATM switch systemxe2x80x9d that realizes hitless switching of a duplexed ATM switch in an apparatus. In this ATM switch system, the number of cells accumulated in an active switch is compared with the number of cells accumulated in a stand-by switch. When the number of cells accumulated in the active switch is larger than the number of cells accumulated in the stand-by switch, reading of cell from the stand-by switch is stopped by the difference in the number of accumulated cells. On the other hand, when the number of cells accumulated in the active switch is smaller than the number of cells accumulated in the stand-by switch, the read address of the stand-by switch is read in advance by the difference in accumulated cell to equalize the amount of the accumulated cell in the stand-by switch to the amount of the accumulated cell in the active switch, thus realizing hitless switching.
FIGS. 1 and 2 show a block diagram showing the xe2x80x9cATM switch systemxe2x80x9d disclosed in Japanese Patent Laid-Open No. 139726/1996. The ATM switch system shown in FIG. 1 comprises a T cell insertion circuit 311 corresponding to the switching control cell, a branch circuit 312, an active switch 320, a stand-by switch 330, and a selecting circuit 341. The active switch 320 comprises a buffer 331, a T cell detection circuit 322, and a detection circuit 323 for the number of residence cells. The stand-by switch 330 comprises a buffer 331, a T cell detection circuit 322, a detection circuit 333 for the number of residence cells, a differential computation circuit 334, and a read control circuit 335.
The ATM switch system shown in FIG. 2 comprises, in addition to the elements constituting the ATM switch system shown in FIG. 1, a threshold comparator circuit 336 provided the stand-by switch 330.
Both the xe2x80x9cATM cell flow controllerxe2x80x9d disclosed in Japanese Patent Laid-Open No. 83529/1997 and the xe2x80x9chitless switch systemxe2x80x9d disclosed in Japanese Patent Laid-Open No. 186575/1996 realize hitless switching of a duplexed transmission path. In both cases, however, phases of input signals of two systems having different phases are equalized to realize hitless switching. Therefore, these cannot be applied to hitless switching of an ATM switch.
In the xe2x80x9cATM switch systemxe2x80x9d disclosed in Japanese Patent Laid-Open No. 139726/1996, during the equalization of the number of cells accumulated in the active switch to the number of cells accumulated in the stand-by switch, when the number of accumulated cells exceeds, only in one switch, the threshold value for the discard low priority class, for an input cell belonging to the discard low priority class, cell discard is performed in the switch system wherein the number of accumulated cells exceeds the threshold value, while, in the other switch system, cell accumulation is performed. Therefore, at the time of the completion of the equalization, the number of cells belonging to the discard low priority class accumulated in one of the switch systems is different from that in the other switch system. This poses a problem that application to an ATM switch having the function of discard priority control cannot realize hitless switching.
In the construction shown in FIG. 2, a circuit for comparison of threshold values is provided. The threshold value used in this circuit is not for discard priority control but for judgement of whether or not the state of the accumulated cells should be equalized, here again posing a problem that hitless switching cannot be realized.
Accordingly, it is an object of the invention to provide a switching system for an ATM switch that, in an ATM switch having the function of discard priority control, can realize hitless switching.
According to a first aspect of the invention, a switching system for an ATM switch, comprises:
an input interface comprising a switching control cell generator for inserting a switching control cell into an input cell, and a branch circuit for branching a signal with the switching control cell inserted therein into two parts which are then output from the switching control cell generator and are input respectively into an active switch and a stand-by switch,
said active switch comprising a cell buffer for accumulating the cell received from the branch circuit, a buffer controller for controlling writing into the cell buffer and reading from the cell buffer, a first active switching control cell detector for detecting the switching control cell from a row of cells received from the branch circuit and notifying the buffer controller of the switch control cell detection, and a second active switching control cell detector for detecting the switching control cell from a row of cells output from the cell buffer and notifying the buffer controller and the stand-by buffer controller of the switching control cell detection,
the stand-by switch comprising a cell buffer for accumulating the cell received from the branch circuit, a buffer controller for controlling writing into the cell buffer and reading from the cell buffer, and a stand-by switching control cell detector for detecting the switching control cell from a row of cells received from the branch circuit and notifying the buffer controller of the switch control cell detection; and
an output interface having a selecting circuit for selecting the output from any one of the active switch and the stand-by switch,
wherein the active buffer controller discriminates the discard priority class of the input cell and controls the write or discard of the input cell according to the number of cells accumulated within the cell buffer and, when the input cell is discarded, notifies the stand-by buffer controller of the discard of the input cell, and, in a period between the receipt of a notification of switching control cell detection from the first active switching control cell detector and the receipt of a notification of switching control cell detection from the second active switching control cell detector, performs, in addition to the discard priority control, the discard control of the corresponding input cell upon a notification of the discard of the input cell from the stand-by buffer control, and
the stand-by buffer controller discriminates the discard priority class of the input cell to control the write or discard of the input cell according to the number of cells accumulated within the cell buffer, and, at the time of discard of the input cell, notifies the active buffer controller of the discard of the input cell, and, further, in a period between the receipt of a notification of switching control cell detection from the stand-by switching control cell detector and the receipt of a notification of switching control cell detection from the second active switching control cell detector, performs, in addition to the discard priority control, the discard control of the corresponding input cell upon the receipt of a notification of the discard of the input cell from the active buffer control, and, upon the receipt of a notification of switching control cell detection from the stand-by switching control cell detection, discards the input switch control cell and all the cells already accumulated within the stand-by cell buffer to empty the cell buffer, and, further, in this case, until the receipt of a notification of switching control cell detection from the second active switching control cell detector, stops reading of cells from the stand-by cell buffer to equalize the cell accumulated within the active cell buffer to the cell accumulated within the stand-by cell buffer.
According to a second aspect of the invention, a switching system for an ATM switch, comprises:
an input interface comprising a switching control cell generator for inserting a switching control cell into an input cell, and a branch circuit for branching a signal with the switching control cell inserted therein into two parts which are then output from the switching control cell generator and are input respectively into an active switch and a stand-by switch,
said active switch comprising a cell buffer for accumulating the cell received from the branch circuit, a buffer controller for controlling writing into the cell buffer and reading from the cell buffer, and a first switching control cell detector for detecting the switching control cell from a row of cells output from the cell buffer and notifying the stand-by buffer controller of the switching control cell detection,
the stand-by switch comprising a cell buffer for accumulating the cell received from the branch circuit, a buffer controller for controlling writing into the cell buffer and reading from the cell buffer, and a second switching control cell detector for detecting the switching control cell from a row of cells received from the branch circuit and notifying the buffer controller of the switch control cell detection; and
an output interface having a selecting circuit for selecting the output from any one of the active switch and the stand-by switch,
wherein the active and stand-by buffer controllers each discriminate the discard priority class of the input cell and control the write or discard of the input cell according to the number of cells accumulated within the active and stand-by cell buffers; when cell discard control is performed in one of the active and stand-by cell buffers, control for discard of the corresponding input cell is performed in the other cell buffer; upon receipt of a notification of switching control cell detection from the second switching control cell detector, the stand-by buffer controller discards all the cells already accumulated within the stand-by cell buffer to empty the cell buffer, and, further, in this case, until the receipt of a notification of switching control cell detection from the first switching control cell detection, stops reading of cells from the stand-by cell buffer to control equalization of cells accumulated within the active and stand-by cell buffers.
According to the invention, when the input cell in one system is discarded, the corresponding cells in the other system is discarded. This can avoid occurrence of cell discard in one system alone and can equalize the cell accumulated in the active cell buffer to the cell accumulated in the stand-by cell buffer.